1. Field of the Invention
The present invention relates to latch circuitry and more particularly to radiation resistant latch circuitry.
2. Related Art
Domino logic latching circuits are known in the art. For example, the latch circuit 100 of FIG. 1 shown here was disclosed in U.S. Pat. No. 5,896,046, xe2x80x9cLatch structure for ripple domino logic,xe2x80x9d Apr. 20, 1999, which is hereby incorporated herein by reference. Latch circuit 100 includes an input stage 10 and a feedback stage 120. In FIG. 1, it is assumed that the data signal D_B comes from a preceding domino logic stage. During an evaluate phase the clock signal goes high and the data signal D_B is held high or driven low by the preceding domino logic stage. With the clock signal high, the latch circuit 100 permits the data signal to drive its latch node 121 high or low. Then, during a precharge phase, the data signal D_B goes high and the clock signal CLK goes low. According to the arrangement shown for circuit 100, with the data and clock signals in their precharge states feedback through inverter 122 will keep the latch node 121 high or low regardless of whether the latch node was driven high or low during evaluation.
Another prior art domino latch circuit is the domino lookaside latch 200 shown in FIG. 2. This circuit improves immunity to noise on the output node OUT by feeding forward to the output node from the inputs, data D_B and clock CLK, through circuit 100 and inverter 201 coupled to feed forward node 211, instead of feeding back from the output node. (In FIG. 2 and other FIG""s herein where circuit reference numbers 100, 100A, 100B, etc. are shown it should be understood that such circuits are instances of circuit 100 shown in FIG. 1. Likewise the same applies to circuit reference numbers 300, 300A, etc. being instances of circuit 300 shown in FIG. 3.)
Another prior art latch circuit 300 is shown in FIG. 3. In this circuit 300, cross coupled inverters 311 and 312 provide a memory cell 310 coupled to the latch node 301, which provides output node OUT. A pair of parallel pass gates 320 controlled by the clock signal CLK and its complement CLK_B are interposed between the latch node 301 and a data signal IN. A single inverter 330 is interposed between the latch node 301 and the output node OUT. According to this arrangement, when the clock signal CLK is high the data signal IN drives the latch node 301 high or low, as the case may be, and when the clock signal is low the memory cell 310 keeps the latch node 301 high or low.
One problem with all these prior art arrangements is that cosmic rays and alpha particles can collide with a latch node and cause it and an output to switch states erroneously. One way that this has been addressed in the past has been to add charge on the latch node. While this solution tends to be effective to prevent erroneous switching caused by alpha particles, it is not very effective against cosmic rays, which have much higher energy.
Another way this has been addressed for a latch of the memory cell type is shown in FIG. 4, which was disclosed in IBM Technical Disclosure Bulletin, volume 30, No. 8, January 1988, Twice Redundant Radiation Hardened Latch, pages 248 through 249, and which is hereby incorporated herein by reference. According to this arrangement, three memory cell latch nodes B1, B2 and B3 are tied together to a single output inverter 401 via respective resistors 411A, 411B and 411C. The resistors are necessarily rather large in order to be effective, so they tend to adversely affect performance of the circuit 400. Therefore a need exists for improvements in radiation immunity for latches.
The foregoing need is addressed in the present invention. In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch""s input circuitry and feedback circuitry coupled to the sublatch""s output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.
Objects, advantages, additional aspects and other forms of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.